ISSN: 2349-5162

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Published in:

Volume 1 Issue 5
October-2014
eISSN: 2349-5162

Unique Identifier

JETIR1405016

Page Number

327-330

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Title

Design and Implementation of H.264/AVC Encoder Using 3D DCT Architecture

ISSN

2349-5162

Cite This Article

"Design and Implementation of H.264/AVC Encoder Using 3D DCT Architecture", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.1, Issue 5, page no.327-330, October-2014, Available :http://www.jetir.org/papers/JETIR1405016.pdf

Abstract

H.264/AVC is a joint project of ITU and MPEG. It provides high quality compression for various services like IP streaming media, SDTV and HDTV broadcast and video on demand etc. Motion estimation, input buffer, summation unit and reference frame section form complex design of H.264/AVC encoder. It is the most advanced video standard. In this paper,H.264/AVC encoder is designed in verilog with better performance and optimized structure. Design is finally implemented on FPGA platform.

Key Words

H.264/AVC,3DDCT,Encoder,Implementation, FPGA,Complexity

Cite This Article

"Design and Implementation of H.264/AVC Encoder Using 3D DCT Architecture", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.1, Issue 5, page no. pp327-330, October-2014, Available at : http://www.jetir.org/papers/JETIR1405016.pdf

Publication Details

Published Paper ID: JETIR1405016
Registration ID: 140239
Published In: Volume 1 | Issue 5 | Year October-2014
DOI (Digital Object Identifier):
Page No: 327-330
ISSN Number: 2349-5162

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Cite This Article

"Design and Implementation of H.264/AVC Encoder Using 3D DCT Architecture", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.1, Issue 5, page no. pp327-330, October-2014, Available at : http://www.jetir.org/papers/JETIR1405016.pdf




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