• M.RAVINDRA KUMAR REDDY
• K.SUDHAKAR

The role of multiplier circuitry in real time applications such as microprocessor and digital processing is very prime. The power handling capacity of a multiplier is a key parameter in designing using VLSI technology because the consumption and dissipation of power is a factor which also effects the performance of multiplier. In present paper a technique called bypassing is implemented in conventional shift-and-add multiplier architecture. This technique eliminates unnecessary switching activities responsible for power consumption and also eliminates unnecessary iteration done in the conventional multiplier whenever a zero is encountered in the multiplication process.

lowpower, multiplier, shift-and-add, ring counter, feeder

"Low power Multiplier Design using bypassing and feeder technique", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.1, Issue 7, page no.821-826, December-2014, Available :http://www.jetir.org/papers/JETIR1407045.pdf

"Low power Multiplier Design using bypassing and feeder technique", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.1, Issue 7, page no. pp821-826, December-2014, Available at : http://www.jetir.org/papers/JETIR1407045.pdf