• Miss Suvina Vinayan
• Prof. Anup R. Nage

The floating point multiplier is extremely important part of many digital signal processing applications. This paper presents the design for a multiplier which computes complex and floating point numbers of 32 bits using Vedic multiplication technique. The Urdhva Tiryagbhyam sutra from Vedic mathematics is used for multiplication. The implementation of the Vedic mathematics and their application to the multiplier ensure substantial reduction of propagation delay which in turn improves speed. The design is capable of handling underflow and overflow cases. The inputs to the multiplier are provided in IEEE 754, 32 bit binary format .

Vedic mathematics, Urdhva Tiryagbhyam sutra, Floating point.

"Design of IEEE 754 Format 32 Bit Complex Floating Point Vedic Multiplier - A Review", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.2, Issue 6, page no.1694-1696, June-2015, Available :http://www.jetir.org/papers/JETIR1506002.pdf

"Design of IEEE 754 Format 32 Bit Complex Floating Point Vedic Multiplier - A Review", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.2, Issue 6, page no. pp1694-1696, June-2015, Available at : http://www.jetir.org/papers/JETIR1506002.pdf