ISSN: 2349-5162

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Published in:

Volume 2 Issue 6
July-2015
eISSN: 2349-5162

Unique Identifier

JETIR1506068

Page Number

2086-2094

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Title

Dual-VDD,Single-Frequency Clocking Methodology for System on Chip

ISSN

2349-5162

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"Dual-VDD,Single-Frequency Clocking Methodology for System on Chip ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.2, Issue 6, page no.2086-2094, July-2015, Available :http://www.jetir.org/papers/JETIR1506068.pdf

Abstract

Abstract— Clock distribution networks synchronize the flow of data signals among synchronous data paths. The design of these networks can dramatically affect system-wide performance and reliability. A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths. Minimum and maximum timing constraints are developed from the relative timing between the localized clock skew and the data paths.

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Cite This Article

"Dual-VDD,Single-Frequency Clocking Methodology for System on Chip ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.2, Issue 6, page no. pp2086-2094, July-2015, Available at : http://www.jetir.org/papers/JETIR1506068.pdf

Publication Details

Published Paper ID: JETIR1506068
Registration ID: 150610
Published In: Volume 2 | Issue 6 | Year July-2015
DOI (Digital Object Identifier): http://www.dx.doi.org/10.5281/zenodo.579685
Page No: 2086-2094
ISSN Number: 2349-5162

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Cite This Article

"Dual-VDD,Single-Frequency Clocking Methodology for System on Chip ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.2, Issue 6, page no. pp2086-2094, July-2015, Available at : http://www.jetir.org/papers/JETIR1506068.pdf




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