• Abhishek Patel
• Vivek Dubey
• Ravimohan

In this work design of a cross coupled topology with switched biasing technique is proposed which can work in high frequency region. The phase noise generated by the voltage controlled oscillator has been reduced by sizing the active devices, because the impact of physical parameter of device is large on the specification of any radio frequency integrated circuit. The proposed design is verified through standard 0.18 µm CMOS process supplied by Tanner’s EDA simulation software tool. Several designs of voltage control oscillator circuits have been implemented for a comparison and verify that the switched biasing does improve frequency and phase noise performance. These results are then compared Simulation results shows an improvement from 114.3 dBc/Hz to -139.6 dBc/Hz at a 1 MHz offset frequency from the 5 GHz carrier when switched biasing. The relative increase in voltage control oscillator’s phase noise performance translates in higher modulation accuracy when used in a transceiver, therefore this increase can be regarded as significant. The power consumption of the simulated VCO is around 746mW

CMOS, Cross-coupled, phase noise, Tanner EDA, VCO

"Design and Analysis of 5GHz Frequency, Low- Phase- Noise, Parasitic Compensated LC Voltage Controlled Oscillator", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.2, Issue 12, page no.214-216, December-2015, Available :http://www.jetir.org/papers/JETIR1512037.pdf

"Design and Analysis of 5GHz Frequency, Low- Phase- Noise, Parasitic Compensated LC Voltage Controlled Oscillator", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.2, Issue 12, page no. pp214-216, December-2015, Available at : http://www.jetir.org/papers/JETIR1512037.pdf