• D.NARESH KUMAR
• GEETHU MOHAN

Abstract:The design complexity in consumer embedded systems has changed to new techniques. The System –on-chip consists of many integrated components of high speed data rates. Intercommunication requirements of SOC uses shared bus or a hierarchy of buses because of their poor scalability,System size, energy efficiency requirements and their shared bandwidth between all the attached hardware cores of final products. To overcome the problems of scalability and complexity we proposed the Networks-On-Chip (NoCs).TheSoCs ,overheads of buses are connected by general-purpose communication architectures. This paper describes that NoCs as a major role in optimizingpower consumption,the performance The performance of can be Enhanced by using data compression technique..

System on chip, System on chip, Network on chip, Network interface, Network Interface compression, Electromagnetic interference, Non Uniform Cache Architecture.

"Design and Optimization of System-on-chip (SOC)", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.2, Issue 12, page no.234-239, December-2015, Available :http://www.jetir.org/papers/JETIR1512041.pdf

"Design and Optimization of System-on-chip (SOC)", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.2, Issue 12, page no. pp234-239, December-2015, Available at : http://www.jetir.org/papers/JETIR1512041.pdf