• Sangamesh Ballur
• Nithya S

A novel of this project is based on the technique system Verilog assertions the power consumed by the RTL design can be optimized [4]. The designed technique supports the designer to boost of his RTL code achieving towards low power design. The designer written codes for the intended technique render to the proposed design specification and get the test bench of his own by coded integration technique [3]. The directive messages generated by the coded technique those are succeed to modify and enhance the code of the design to be optimize the power consumption of the design. The main idea behind to this approach is keep observing all the design signal. so, this approach is a dependent design technique, as it depends on the specifications of the design. This coded technique catches the targeted signals of intended input [1]. Then it shows the wrongly setting signals those may absorb extra wasted power. This approach can be applied and inserted in any of the verification framework as the universal verification methodology (UVM), to combine the optimized power features of this technique with the features of used framework. Through utilizing this technique the power consumed by the design is extremely optimized as it receives all remaining design signals that eat up extra wasted power. This project shows how to utilize the proposed technique about every design specifications and also afford technique code itself as a simple case study of RTL [3]. As well, it also assign resultant command or instructions messages and presents a difference between the power consumed before and after the alteration of the RTL code bestow to the command messages of the coded technique.

System Verilog Assertions, Verification Environment, RTL, Test Cases, Universal Verification Methodology.

"A Novel Approach for Optimizing RTL Power using System Verilog Assertions", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.4, Issue 5, page no.266-268, May-2017, Available :http://www.jetir.org/papers/JETIR1705055.pdf

"A Novel Approach for Optimizing RTL Power using System Verilog Assertions", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.4, Issue 5, page no. pp266-268, May-2017, Available at : http://www.jetir.org/papers/JETIR1705055.pdf