JETIREXPLORE- Search Thousands of research papers



Published in:

Volume 5 Issue 1
January-2018
eISSN: 2349-5162

Unique Identifier

JETIR1801161

Page Number

802-807

Share This Article


Title

A Pipelined FFT Architecture to ProcessTwo Independent Data Streams

ISSN

2349-5162

Cite This Article

"A Pipelined FFT Architecture to ProcessTwo Independent Data Streams ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 1, page no.802-807, January-2018, Available :http://www.jetir.org/papers/JETIR1801161.pdf

Abstract

This project proposes the multiple independent FFT computation of two independent data stream is introduced. Multipath delay communicator FFT architecture is the basis of proposed architecture. In time FFT and in frequency FFT it has N/2-point decimation to process the odd and even samples of two data streams separately. The bit reversal operation is performed by the architecture itself is the main feature of the architecture. So without any dedicated bit reversal circuit the outputs are generated in normal order. By interleaving the data the bit reversal operation is performed by the shift registers in the FFT architecture. So high throughput and lower number of register is necessary for the proposed architecture. System throughput is a key factor influencing performance in wireless communication. Nowadays, many applications require simultaneous computation of multiple independent fast Fourier transform (FFT) operations with their outputs in natural order. Therefore, this brief presents a novel pipelined FFT processor for the FFT computation of two independent data streams. The proposed architecture is based on the multipath delay commutator FFT architecture. It has an N/2-point decimation in time FFT and an N/2-point decimation in frequency FFT to process the odd and even samples of two data streams separately. The main feature of the architecture is that the bit reversal operation is performed by the architecture itself, so the outputs are generated in normal order without any dedicated bit reversal circuit. The bit reversal operation is performed by the shift registers in the FFT architecture by interleaving the data. Therefore, the proposed architecture requires a lower number of registers and has high throughput.

Key Words

Fast Fourier Transform (FFT), Multiple Input Multiple Output (MIMO), Pipelined FFT.

Cite This Article

"A Pipelined FFT Architecture to ProcessTwo Independent Data Streams ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 1, page no. pp802-807, January-2018, Available at : http://www.jetir.org/papers/JETIR1801161.pdf

Publication Details

Published Paper ID: JETIR1801161
Registration ID: 180238
Published In: Volume 5 | Issue 1 | Year January-2018
DOI (Digital Object Identifier):
Page No: 802-807
ISSN Number: 2349-5162

Download Paper

Preview Article

Download Paper




Cite This Article

"A Pipelined FFT Architecture to ProcessTwo Independent Data Streams ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 1, page no. pp802-807, January-2018, Available at : http://www.jetir.org/papers/JETIR1801161.pdf




Preview This Article


Downlaod

Click here for Article Preview