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Published in:

Volume 5 Issue 1
January-2018
eISSN: 2349-5162

Unique Identifier

JETIR1801162

Page Number

808-813

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Title

A POLAR CODE SUCCESSIVE CANCELLATION DECODER IMPLIMENTATION THROUGH A COMBINATIONAL LOGIC CIRCUIT

ISSN

2349-5162

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"A POLAR CODE SUCCESSIVE CANCELLATION DECODER IMPLIMENTATION THROUGH A COMBINATIONAL LOGIC CIRCUIT", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 1, page no.808-813, January-2018, Available :http://www.jetir.org/papers/JETIR1801162.pdf

Abstract

This paper proposes a high-throughput energy efficient Successive Cancellation (SC) decoder architecture for polar codes based on combinational logic. The proposed combinational architecture operates at relatively low clock frequencies compared to sequential circuits, but takes advantage of the high degree of parallelism inherent in such architectures to provide a favourabletrade-off between throughput and energy efficiency at short to medium block lengths. At longer block lengths, the paper proposes a hybrid-logic SC decoder that combines the advantageous aspects of the combinational decoder with the low complexity nature of sequential-logic decoders. Performance characteristics on ASIC and FPGA are presented with a detailed power consumption analysis for combinational decoders. Finally, the paper presents an analysis of the complexity and delay of combinational decoders, and of the throughput gains obtained by hybridlogic decoders with respect to purely synchronous architectures.Nowadays, many applications require simultaneous computation of multiple independent fast Fourier transform (FFT) operations with their outputs in natural order. Therefore, this brief presents a novel pipelined FFT processor for the FFT computation of two independent data streams. The proposed architecture is based on the multipath delay commutator FFT architecture. It has an N/2-point decimation in time FFT and an N/2-point decimation in frequency FFT to process the odd and even samples of two data streams separately. The main feature of the architecture is that the bit reversal operation is performed by the architecture itself, so the outputs are generated in normal order without any dedicated bit reversal circuit. The bit reversal operation is performed by the shift registers in the FFT architecture by interleaving the data. Therefore, the proposed architecture requires a lower number of registers and has high throughput.

Key Words

A POLAR CODE SUCCESSIVE CANCELLATION DECODER IMPLIMENTATION THROUGH A COMBINATIONAL LOGIC CIRCUIT

Cite This Article

"A POLAR CODE SUCCESSIVE CANCELLATION DECODER IMPLIMENTATION THROUGH A COMBINATIONAL LOGIC CIRCUIT", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 1, page no. pp808-813, January-2018, Available at : http://www.jetir.org/papers/JETIR1801162.pdf

Publication Details

Published Paper ID: JETIR1801162
Registration ID: 180239
Published In: Volume 5 | Issue 1 | Year January-2018
DOI (Digital Object Identifier):
Page No: 808-813
ISSN Number: 2349-5162

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Cite This Article

"A POLAR CODE SUCCESSIVE CANCELLATION DECODER IMPLIMENTATION THROUGH A COMBINATIONAL LOGIC CIRCUIT", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 1, page no. pp808-813, January-2018, Available at : http://www.jetir.org/papers/JETIR1801162.pdf




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