• Mr. A.CHAKRADHAR
• Mrs.A.KARUNA SRI

A new test generation methodology is proposedthat takes advantage of shared memory multi-core systems. Appropriateparallelization of the main steps of ATPG allocatesresources in order to minimize workload duplication and multithreadingrace contention, often encountered in parallel implementations.Recent works on ATPG parallelization for on-chip multicoreenvironments exploit a variety and, often mixture, of parallelism dimensions such as fault parallelism, structural (circuit) parallelism, and algorithmic (including search-space) parallelism. Moreover, the goal of utilizing parallelism often varies.The proposed approach ensures that the obtainedacceleration grows linearly with the number of processing coresand, at the same time, keeps the test set size close to that obtainedby serial ATPG. The experimental results demonstrate that theproposed methodology achieves higher degree of speed-up thancomparable state-of-the-art multi-core based tools, while maintainssimilar test set sizes.

ATPG; Parallel Processing; Multi-core systems

"MEMORY SHARING & UTILIZATION AMONG MULTIPLE PROCESSING UNITS TO IMPROVE THE PERFORMANCE OF ATPG PROCESS THROUGH HDL", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 1, page no.820-825, January-2018, Available :http://www.jetir.org/papers/JETIR1801164.pdf

"MEMORY SHARING & UTILIZATION AMONG MULTIPLE PROCESSING UNITS TO IMPROVE THE PERFORMANCE OF ATPG PROCESS THROUGH HDL", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 1, page no. pp820-825, January-2018, Available at : http://www.jetir.org/papers/JETIR1801164.pdf