• Priyanka Rakshe
• Pankaj Prajapati

System on Chip (SoC) allows millions of transistors to be integrated on single chip. Traditional SoC has bus-based architecture for communication which limits the processing speed. Now a day’s in Silicon industries there is emerging concept of Network on Chip (NoC) to decouple communication from computations. The router is a backbone of NoC, hence the efficient design of router is essential to enhance the performance of the system. In present work, we focus on a router input-output protocol design. The proposed system includes virtual cut through a mechanism for close loop communication. Router 1x3 has single input port and three output ports. Top-level architecture designed with sub-modules like FIFO, FSM, Synchronizer and Register using Verilog language. Routers RTL design analyzed and verified using Xilinx 14.5 Spartan-3E- xc3s100e FPGA family. Simulation of RTL design carried on ISim simulator. Code coverage observed on Questasim. Power utilization observed on XPower, it is 80mW.

Network on Chip (NoC), Router, FIFO, FSM, Synchronizer, Register, Verilog

"Router1x3 Protocol design with virtual cut through Mechanism for Network on Chip (NoC) ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 4, page no.1102-1106, April-2018, Available :http://www.jetir.org/papers/JETIR1804221.pdf

"Router1x3 Protocol design with virtual cut through Mechanism for Network on Chip (NoC) ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 4, page no. pp1102-1106, April-2018, Available at : http://www.jetir.org/papers/JETIR1804221.pdf