• Mir Mohammad Burhan
• Nadeem Tariq Beigh
• Sandeep Kumar Singh

In this paper the design of 3rd order decimation filter with a decimation factor 16 is presented using the FDA tool of DSP system toolbox of MATLAB. The filter is realized using Simulink. The filter is optimized for the size of adders and subtractors in terms of the word length by reducing the word length of consecutive adders to save area and computational complexity. The designed filter is converted to a Verilog RTL using the HDL coder in MATLAB. This filter is implemented in Xilinx and simulated in ISIM simulator for white noise, impulse and step response for 1000 samples. An optimized Verilog RTL implementation of the same filter is also presented. This optimized code is less complex and understandable and has the same functionality with lesser resource utilization.

Decimation filters, CIC filters, Verilog RTL, Filter design, Filter implementation.

"3rd ORDER CIC DECIMATION FILTER DESIGN & IMPLEMENTATION", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 5, page no.720-727, May-2018, Available :http://www.jetir.org/papers/JETIR1805541.pdf

"3rd ORDER CIC DECIMATION FILTER DESIGN & IMPLEMENTATION", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 5, page no. pp720-727, May-2018, Available at : http://www.jetir.org/papers/JETIR1805541.pdf