• BHARATH C N
• Dr. B S KARIYAPPA

The basic core unit of any sequential digital system is a Flipflop. The most widely used Transmission Gate (TG FF) based flip flop suffer from excessive work load on the clock signal. In this paper low power logically reduced True Single Phase Clock (TSPC) Flipflop using Dual Threshold (DT) technology is proposed. TSPC Flipflops reduces overhead on the clock signal. Logically Reduced Flip Flop (LRFF) is the optimized TSPC FF obtained by structure reduction method. Sub-threshold leakage is the dominating leakage currents over other leakage currents. Sub threshold leakage power can be reduced by using a high threshold voltage on discharging path. The proposed low power logically reduced TSPC using dual threshold technology reduces the overall power by 40.3% and power-delay product (PDP) by 34.8% compared to LRFF. The designs are implemented using cadence virtuoso 90nm technology.

TSPC, Dual threshold CMOS, TG FF, LRFF, Leakage power, 90nm technology

"Low Power Logically Reduced TSPC Flipflop Design using Dual Threshold CMOS Technology", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 5, page no.813-816, MAY-2018, Available :http://www.jetir.org/papers/JETIR1805740.pdf

"Low Power Logically Reduced TSPC Flipflop Design using Dual Threshold CMOS Technology", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 5, page no. pp813-816, MAY-2018, Available at : http://www.jetir.org/papers/JETIR1805740.pdf