• Kalluri Manideepthi
• K. Niranjan Reddy
• N. Neelima

The increasing demand of low complexity and error-tolerant design in signal processing systems is a reliability issue at ground level. The complex circuit is consistently affected by soft errors in modern electronic circuits. Fast Fourier transforms (FFTs) plays a key role in many communication and signal processing systems. Different algorithms have been used in earlier techniques for achieving fault tolerant coverage design. In real time application systems, numbers of blocks operating in parallel are frequently used. The proposed work exploits a technique to implement fault tolerance parallel FFT with reduced low complexity of circuit area and power. To reduce the area we used Vedic Multiplier in place of Booth’s Multiplier. Low power and area efficient adder and multiplier have always been a fundamental requirement of high-performance processors and systems. To design a Fast Fourier Transform (FFT) its speed greatly depends on the multiplier and adder. Carry select adder is one of the fast adders used in many processors to increase their speed with reduced size and low power, reduced complexity. Carry Select Adder (CSLA) that uses multiple pairs of Ripple Carry Adder (RCA) uses moderate delay, larger area and high power. Vedic multiplier is an ancient form of multiplication which performs the multiplication operation faster. It uses 16-sutras. Here we used the Urdhva Tiryakbhyam Sutra, to reduce the number of steps in the multiplication method. So the time, area and delay are reduced. Vedic multiplier and carry select adder can be used to design a Fast Fourier Transform (FFT) which produces an output at a very faster time and the delay, area can be reduced.

: FFTs, Vedic Multiplier, Urdhva Tiryakbhyam Sutra, Xilinx

"Advanced Technology using Vedic Multiplier for Efficient Area in Parallel FFTs", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 7, page no.1157-1166, July-2018, Available :http://www.jetir.org/papers/JETIR1807897.pdf

"Advanced Technology using Vedic Multiplier for Efficient Area in Parallel FFTs", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 7, page no. pp1157-1166, July-2018, Available at : http://www.jetir.org/papers/JETIR1807897.pdf