• C.Akhila
• G. Ravi Kumar

Power dissipation in VLSI circuits has become increasingly important for modern portable devices. Adiabatic is a novel energy conserving logic for ultra-low power circuits. Adiabatic logic is energy efficient and less logic overhead. Fully adiabatic and partial energy recovery adiabatic circuits are two major logic's which work for wide range of frequency. Sub-threshold adiabatic logic is a novel approach for low energy consumption and low speed digital circuits which work for low frequency. A Johnson's ring counter circuit is designed using static CMOS and SAL using CADENCE 45nm technology. Hence in this proposed system the Johnson’s ring counter is tested and the power dissipation is obtained.

cadence (virtuoso) 6.1

"DESIGN OF SUB-THRESHOLD ADIABATIC LOGIC BASED JOHNSON'S RING COUNTER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 9, page no.284-293, October-2018, Available :http://www.jetir.org/papers/JETIR1809692.pdf

"DESIGN OF SUB-THRESHOLD ADIABATIC LOGIC BASED JOHNSON'S RING COUNTER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 9, page no. pp284-293, October-2018, Available at : http://www.jetir.org/papers/JETIR1809692.pdf