• SIVAKUMAR S A
• GEETHA S
• AMUTHA A

A rapid growth of portable battery operated devices has made low power IC design a priority in recent years. The Embedded SRAM units have become an integral part in modern SoCs. Conventional SRAM cell designs are power hungry and poor performers in this new fast mobile computing. In this paper, low power SRAM cell designs have been analyzed for power consumption, write delay and write power delay product. Gated VDD and MTCMOS design techniques have been employed to reduce the power consumed by the SRAM cell. These designs are compared with the conventional 6T SRAM cell. The result show that the MTCMOS based SRAM cell is the best performer in terms of power consumption and write delay. It is less power than the conventional 6T SRAM cell. Furthermore, the MTCMOS based SRAM cell is faster than the conventional 6T SRAM cell. The Gated VDD SRAM cell also less power than the conventional 6T SRAM cell and is faster than the conventional 6T SRAM cell.

"Design and Analysis of Low Power 6T SRAM Cell", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 10, page no.247-252, October-2018, Available :http://www.jetir.org/papers/JETIR1810733.pdf

"Design and Analysis of Low Power 6T SRAM Cell", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 10, page no. pp247-252, October-2018, Available at : http://www.jetir.org/papers/JETIR1810733.pdf