• Chappa Supriya

There is a growing interest in multi-bit Error Correction Codes (ECCs) to protect SRAM memories. This has been caused by the increased number of multiple errors that memories suffer as technology scales. To protect an SRAM memory, an ECC has to be decodable in parallel and with low latency. Among the codes proposed for memory protection are Orthogonal Latin Square (OLS) codes that provide low latency decoding and a modular construction. It is more effective to provide different degrees of error correction for the different bits. This is done with Unequal Error Protection (UEP) codes. In this paper, UEP codes are derived from Double Error Correction (DEC) Orthogonal Latin Square (OLS) codes. The results show that the implemented with lower decoding delay is reduced 30% than traditional SEC-DED codes and with a cost similar to that of both DEC OLS and SEC-DED codes. The Proposed encoder and decoder are done by Verilog HDL and Simulated and synthesized by Xilinx 14.3 tool.

OLS cods, SEC-DED codes, OS-MLD codes, UPE codes.

"Efficient implementation of double error detection and correcting OLS codes", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 10, page no.27-30, October-2018, Available :http://www.jetir.org/papers/JETIR1810785.pdf

"Efficient implementation of double error detection and correcting OLS codes", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 10, page no. pp27-30, October-2018, Available at : http://www.jetir.org/papers/JETIR1810785.pdf