• Muddapu Harika
• E. Lakshmi Prasad

The main objective of this project is to reduce the application test data time and test data volume using customized LFSR for combinational ATPG and sequential ATPG circuits. There are many existing standard LFSRs are used for generating the test patterns but the proposed method able to reduce the application test data time and test data volume by selecting the appropriate seed value by using different characteristic polynomials. The main purpose of customized LFSR is to generate a limited number of bits to achieve test data compression. An LFSR will produce a pseudo-random sequence with a maximum length of (2n-1) states (where n is the number of stages). The number of states can be reduced by selecting the appropriate characteristic polynomial for LFSR. The test application data and data volume can be reduced by selecting the appropriate seed value. Here, in this paper customized LFSR is designed with respect to 4-bit, 8-bit and 16-bit for all combinational circuits.

LFSR, Test compression, characteristic polynomial, data volume.

"Optimized Test Application Time and Test Data Volume Using LFSR for Combinational Circuits", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 10, page no.71-77, October-2018, Available :http://www.jetir.org/papers/JETIR1810790.pdf

"Optimized Test Application Time and Test Data Volume Using LFSR for Combinational Circuits", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 10, page no. pp71-77, October-2018, Available at : http://www.jetir.org/papers/JETIR1810790.pdf