UGC Approved Journal no 63975(19)

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Published in:

Volume 5 Issue 10
October-2018
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR1810845


Registration ID:
187514

Page Number

437-442

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Title

An implementation of Viterbi algorithm on an FPGA for the design of viterbi decoder

Abstract

The availability of wireless technology has revolutionized the way communication is done in the present scenario. With this increased accessibility comes increased dependence on the underlying systems to transmit information both quickly and accurately. Because the communications channels in ‘wireless’ systems can introduce more errors than in “wired” systems, voice and data must use forward error correction coding to reduce the probability of channel effects corrupting the information being transmitted. One such code which is based on the forward error correction (FEC) technique is the convolutional code. Convolutional codes can be defined as a set of block codes with memory where the ‘n’ encoder outputs at any given point of time not only depends on ‘k’ inputs but also depends on ‘m’ memory elements. The optimum decoding algorithm used for decoding the convolutional codes is the Viterbi algorithm. It is limited to smaller constraint lengths but it has a greater advantage of using maximum likelihood decoding. Though various platforms can be used for realizing this implementation, we consider that using an FPGA is advantageous. FPGAs are a technology that gives the designer flexibility of a programmable solution, minimize the overall cost and enhance the adaptability with optimal device utilization by conserving both board space and system power. In this project, the Viterbi algorithm is being implemented on an FPGA, Xilinx Spartan 6 XC6SLX45, on designing platform Xilinx ISE design Suite 14.5 and ChipScope Pro to decode error control codes that are used to enhance the performance of digital communication system by reducing the probability of channel effects.

Key Words

Convolutional Codes, FPGA, Wireless Systems, Viterbi Algorithm, Xilinx Spartan 6

Cite This Article

"An implementation of Viterbi algorithm on an FPGA for the design of viterbi decoder", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 10, page no.437-442, October-2018, Available :http://www.jetir.org/papers/JETIR1810845.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"An implementation of Viterbi algorithm on an FPGA for the design of viterbi decoder", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 10, page no. pp437-442, October-2018, Available at : http://www.jetir.org/papers/JETIR1810845.pdf

Publication Details

Published Paper ID: JETIR1810845
Registration ID: 187514
Published In: Volume 5 | Issue 10 | Year October-2018
DOI (Digital Object Identifier):
Page No: 437-442
Country: hyderabad, Telangana, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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