UGC Approved Journal no 63975(19)

ISSN: 2349-5162 | ESTD Year : 2014
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Published in:

Volume 5 Issue 11
November-2018
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR1811A87


Registration ID:
192365

Page Number

672-683

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Title

DESIGN AND IMPLEMENTATION OF 4-BIT SHIFT REGISTER USING DOMINO AND DOIND LOGIC TECHNIQUES

Abstract

Dynamic CMOS logic circuits are utilised in the VLSI ICs to get the high performance of systems. But the parameter variations are serious problems in the deep sub-micron Technology by scaling down dimensions of transistors. Power consumption ,delay and leakage current are the performance parameters of any logic circuit. The performance of circuit reduces by the increment of power, delay and leakage current. To overcome these transistor parameter variations in nanometer technology design should be conscious of fluctuations. In this DOIND logic design and domino logic design are used to study the variances issue. DOIND logic is designed from domino logic. DOIND logic design minimises leakage current as well as it minimises the variances issue with less delay disadvantage. Several processes, Voltages and Temperatures (PVT) variances studied at 60nm technology node for a domino logic and DOIND logic for Serial in Serial out (SISO) 4-BIT Shift Register, Parallel in Serial out (PISO) 4-BIT Shift Register and Parallel in Parallel out (PIPO) 4-BIT Shift Register, using Tanner EDA tool.

Key Words

DOIND logic, Leakage current, PVT, nanometer Technology, domino, Scaling

Cite This Article

"DESIGN AND IMPLEMENTATION OF 4-BIT SHIFT REGISTER USING DOMINO AND DOIND LOGIC TECHNIQUES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 11, page no.672-683, November-2018, Available :http://www.jetir.org/papers/JETIR1811A87.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"DESIGN AND IMPLEMENTATION OF 4-BIT SHIFT REGISTER USING DOMINO AND DOIND LOGIC TECHNIQUES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 11, page no. pp672-683, November-2018, Available at : http://www.jetir.org/papers/JETIR1811A87.pdf

Publication Details

Published Paper ID: JETIR1811A87
Registration ID: 192365
Published In: Volume 5 | Issue 11 | Year November-2018
DOI (Digital Object Identifier):
Page No: 672-683
Country: ONGOLE, ANDHRA PRADESH, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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