UGC Approved Journal no 63975(19)

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Published in:

Volume 5 Issue 5
May-2018
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR18IC032


Registration ID:
181447

Page Number

142-148

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Title

OVERVIEW OF DESIGN OF COMBINATIONAL LOGIC CIRCUIT FOR LOW POWER VLSI APPLICATION

Abstract

Combinational logic circuits are one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. Combinational logic circuit suitable for various high speed, low power, and compact VLSI implementations. However area and speed are two conflicting constraints. So improving speed results always in larger areas. We tried to find out the best trade off solution among the both of them. In this paper we have designed different adders and compare their speed and complexity of circuit i.e. the area occupied. This paper described the comparative performance of 1-bit full adder designed using TANNER EDA

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"OVERVIEW OF DESIGN OF COMBINATIONAL LOGIC CIRCUIT FOR LOW POWER VLSI APPLICATION", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 5, page no.142-148, May-2018, Available :http://www.jetir.org/papers/JETIR18IC032.pdf

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2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"OVERVIEW OF DESIGN OF COMBINATIONAL LOGIC CIRCUIT FOR LOW POWER VLSI APPLICATION", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 5, page no. pp142-148, May-2018, Available at : http://www.jetir.org/papers/JETIR18IC032.pdf

Publication Details

Published Paper ID: JETIR18IC032
Registration ID: 181447
Published In: Volume 5 | Issue 5 | Year May-2018
DOI (Digital Object Identifier):
Page No: 142-148
Country: Nagpur, Maharashtra, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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