• S.Spandana
• P.Naseema
• P.Kailash
• G.Dhanalakshmi
• K.Prasanth Kumar

In this paper, we propose a multiplexer circuit with less number of MOSFETs in CMOS technology. Using this multiplexer circuit , a full adder circuit was also designed and employ these multiplexer and full adder in efficient circuit designs. We carry out a detailed comparative study for a enhanced CMOS circuit uses RFET logic, which shows the low transistor count , less number of nodes formed and less simulation time while exhibiting similar functionality as compared with the CMOS reference design. We further propose a novel design for a 1-bit arithmetic logic unit-based on RFET structure which uses the multiplexer and full adder circuit(which are designed using the enhanced CMOS designs) with the less number of transistors used , less number of nodes formed and less simulation time as compared with the contemporary CMOS version. The performance of the design is simulated using the TANNER TOOLS v16.0.

Functionally enhanced logic gates, Multi-independent gate reconfigurable field-effect transistor(MIGRFET), RFET, reconfigurable transistor, silicon nanowire (SiNW) transistor, three-independent gate field-effect transistor (TIGFET), Multiplexer, Full Adder.

"DESIGNING EFFICIENT CIRCUIT BASED ON RUN TIME RECONFIGURABLE FIELD EFFECT TRANSISTORS USING ENHANCED CMOS DESIGN", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 3, page no.1620-1625, March-2020, Available :http://www.jetir.org/papers/JETIR2003234.pdf

"DESIGNING EFFICIENT CIRCUIT BASED ON RUN TIME RECONFIGURABLE FIELD EFFECT TRANSISTORS USING ENHANCED CMOS DESIGN", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 3, page no. pp1620-1625, March-2020, Available at : http://www.jetir.org/papers/JETIR2003234.pdf