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Published in:

Volume 7 Issue 3
March-2020
eISSN: 2349-5162

Unique Identifier

JETIR2003316

Page Number

91-95

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Title

DESIGN OF 64 BIT VEDIC MULTIPLIER USING CARRY LOOK AHEAD ADDER

ISSN

2349-5162

Cite This Article

"DESIGN OF 64 BIT VEDIC MULTIPLIER USING CARRY LOOK AHEAD ADDER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 3, page no.91-95, March-2020, Available :http://www.jetir.org/papers/JETIR2003316.pdf

Abstract

This paper proposed the design of 64 bit vedic multiplier using vedic mathematics based on 16 sutras.The main aim of VLSI is to optimize any type of digital architecture. Multiplication is an important fundamental function in arithmetic logic operation. Computational performance of DSP system is limited by its multiplication performance, multiplication dominates the execution time of most DSP algorithms. our work is to develop the 64-bit vedic multiplier using carry look ahead adder technique.

Key Words

Carry look ahead adder , Vedic multiplier

Cite This Article

"DESIGN OF 64 BIT VEDIC MULTIPLIER USING CARRY LOOK AHEAD ADDER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 3, page no. pp91-95, March-2020, Available at : http://www.jetir.org/papers/JETIR2003316.pdf

Publication Details

Published Paper ID: JETIR2003316
Registration ID: 230032
Published In: Volume 7 | Issue 3 | Year March-2020
DOI (Digital Object Identifier):
Page No: 91-95
ISSN Number: 2349-5162

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Cite This Article

"DESIGN OF 64 BIT VEDIC MULTIPLIER USING CARRY LOOK AHEAD ADDER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 3, page no. pp91-95, March-2020, Available at : http://www.jetir.org/papers/JETIR2003316.pdf




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