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Published in:

Volume 7 Issue 5
May-2020
eISSN: 2349-5162

Unique Identifier

JETIR2005104

Page Number

737-741

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Title

POWER OPTIMIZED SELF TEST CRUSOE PROCESSOR WITH REVERSIBLE LOGIC GATES USING ENHANCED MIPS AND VLIW ARCHITECTURES

ISSN

2349-5162

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"POWER OPTIMIZED SELF TEST CRUSOE PROCESSOR WITH REVERSIBLE LOGIC GATES USING ENHANCED MIPS AND VLIW ARCHITECTURES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 5, page no.737-741, May-2020, Available :http://www.jetir.org/papers/JETIR2005104.pdf

Abstract

The main objective of this project is to implement a novel processor for small-scale (minor) and large-scale (major) applications with low dense and low power consumption. In this, well-tuned pipelined architecture and enhanced power control schemes are introduced using modified MIPS (Micro Processor without Inter locked stages), VLIW (Very Long Instruction Word) and PFAL (Positive feed Back Adiabatic Logic) techniques along with BIST (Built in Self-Test) capability. Online and more accurate BIST is implemented with less processing time. This project is designed in such a way that; it is useful for both long and short distance; wired and wireless communications for both Synchronous and Asynchronous modes.

Key Words

MIPS, BIST, VLIW, PFAL, L.F.S.R (Linear Feed Back Shift Register), GALS (Global Asynchronous Local Synchronous), ILP (Instruction Level Parallelism)

Cite This Article

"POWER OPTIMIZED SELF TEST CRUSOE PROCESSOR WITH REVERSIBLE LOGIC GATES USING ENHANCED MIPS AND VLIW ARCHITECTURES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 5, page no. pp737-741, May-2020, Available at : http://www.jetir.org/papers/JETIR2005104.pdf

Publication Details

Published Paper ID: JETIR2005104
Registration ID: 231675
Published In: Volume 7 | Issue 5 | Year May-2020
DOI (Digital Object Identifier):
Page No: 737-741
ISSN Number: 2349-5162

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Cite This Article

"POWER OPTIMIZED SELF TEST CRUSOE PROCESSOR WITH REVERSIBLE LOGIC GATES USING ENHANCED MIPS AND VLIW ARCHITECTURES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 5, page no. pp737-741, May-2020, Available at : http://www.jetir.org/papers/JETIR2005104.pdf




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