• Ravi Kumar Jangir
• Namrata Joshi

In most of the digital systems counter is a basic and essential component so it is important to design an efficient counter in terms of delay and power. In this paper BICMOS logic has been used for the implementation of 4-bit synchronous counter. BICMOS is the combination of CMOS and Bipolar transistors and the purpose of choosing this logic for designing is to combine the advantages of both Bipolar and CMOS transistor logic. Latch up problem can be completely eliminated by using BICMOS logic. Cadence Virtuoso schematic editor is used to implement the proposed circuit and Cadence Virtuoso analog design environment is used for the simulation process. The estimated power for the proposed counter circuit is 85.07 μw and delay is 18.27 ns.

BICMOS, Master-Slave D flip flop, Latch up.

"Design of High Speed Synchronous Counter Using BICMOS Logic", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 5, page no.747-752, May 2020, Available :http://www.jetir.org/papers/JETIR2005418.pdf

"Design of High Speed Synchronous Counter Using BICMOS Logic", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 5, page no. pp747-752, May 2020, Available at : http://www.jetir.org/papers/JETIR2005418.pdf