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Published in:

Volume 7 Issue 7
July-2020
eISSN: 2349-5162

Unique Identifier

JETIR2007276

Page Number

2157-2162

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Title

VLSI Architecture for 8-bit Reversible Arithmetic Logic Unit based on Programmable Gate

ISSN

2349-5162

Cite This Article

"VLSI Architecture for 8-bit Reversible Arithmetic Logic Unit based on Programmable Gate", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 7, page no.2157-2162, July-2020, Available :http://www.jetir.org/papers/JETIR2007276.pdf

Abstract

Reversible computing spans computational models that are both forward and backward deterministic. These models have applications in program inversion and bidirectional computing, and are also interesting as a study of theoretical properties. A reversible computation does, thus, not have to use energy, though this is impossible to avoid in practice, due to the way computers are build. It is, however, not always obvious how to implement reversible computing systems. The restriction to avoid information loss imposes new design criteria that need to be incorporated into the design; criteria that do not follow directly from conventional models. In this paper, investigate garbage-free reversible central processing unit computing systems to physical gate-level implementation. Arithmetic operations are a basis for many computing systems, so a proposed the design of adder, sub tractor, multiplexer, encoder and work towards a reversible circuit for general circuit are important new circuits. In all design implemented Xilinx software and simulated VHDL text bench.

Key Words

Reversible Gates, Arithmetic Logic Unit (ALU), Ancilla Input, Delay

Cite This Article

"VLSI Architecture for 8-bit Reversible Arithmetic Logic Unit based on Programmable Gate", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 7, page no. pp2157-2162, July-2020, Available at : http://www.jetir.org/papers/JETIR2007276.pdf

Publication Details

Published Paper ID: JETIR2007276
Registration ID: 235402
Published In: Volume 7 | Issue 7 | Year July-2020
DOI (Digital Object Identifier):
Page No: 2157-2162
ISSN Number: 2349-5162

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Cite This Article

"VLSI Architecture for 8-bit Reversible Arithmetic Logic Unit based on Programmable Gate", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 7, page no. pp2157-2162, July-2020, Available at : http://www.jetir.org/papers/JETIR2007276.pdf




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