• Abhishek Jadhav

Since last five decades, research and development has taken place in fault tolerant microprocessor. There are increasing reliability issues for embedded systems in aerospace applications. Not only aerospace but telephone switching systems, industrial embedded systems also face this issue. In this paper, we will discuss how various processors tackled Single-Event Upset by various mitigation techniques like SEC/DED ECC, double modular and triple modular redundancy, parity, and even use of fault tolerant functional unit.

Single-Event Effect, Single-Event Upset, Modular redundancy, Error correcting code, Arithmetic Login Unit, Reduced Instruction Set Computer

"TACKLING OF SINGLE-EFFECT UPSET IN MICROPROCESSOR-BASED ARCHITECTURE", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 7, page no.2246-2248, July-2020, Available :http://www.jetir.org/papers/JETIR2007289.pdf

"TACKLING OF SINGLE-EFFECT UPSET IN MICROPROCESSOR-BASED ARCHITECTURE", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 7, page no. pp2246-2248, July-2020, Available at : http://www.jetir.org/papers/JETIR2007289.pdf