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"Implementation of Power Area Efficient 32-Bit Approximate Multiplier with Improved Accuracy", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.8, Issue 1, page no.636-641, January-2021, Available :http://www.jetir.org/papers/JETIR2101087.pdf

• Sonu Pawar
• Prof. Manish Gupta

Approximate computing has received significant attention as a promising strategy to enhance performance of multiplication. Various arithmetic operations such as multiplication addition, subtraction are important part of digital circuit to speed up the computation speed of processor. This paper presents 32 bit approximate multiplier for high speed and low delay for advance digital signal processing. Previous it is designed at 16 bit for various applications. Research work is focus on hardware-level approximation by introducing the partial product perforation technique and dadda multiplier for designing approximate multiplication circuits. Xilinx 14.7 is used to implementation with verilog programming language.

Approximate, Dadda, Multiplier, Verilog, Speed

"Implementation of Power Area Efficient 32-Bit Approximate Multiplier with Improved Accuracy", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.8, Issue 1, page no. pp636-641, January-2021, Available at : http://www.jetir.org/papers/JETIR2101087.pdf