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Published in:

Volume 8 Issue 1
January-2021
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR2101087


Registration ID:
305004

Page Number

636-641

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Title

Implementation of Power Area Efficient 32-Bit Approximate Multiplier with Improved Accuracy

Abstract

Approximate computing has received significant attention as a promising strategy to enhance performance of multiplication. Various arithmetic operations such as multiplication addition, subtraction are important part of digital circuit to speed up the computation speed of processor. This paper presents 32 bit approximate multiplier for high speed and low delay for advance digital signal processing. Previous it is designed at 16 bit for various applications. Research work is focus on hardware-level approximation by introducing the partial product perforation technique and dadda multiplier for designing approximate multiplication circuits. Xilinx 14.7 is used to implementation with verilog programming language.

Key Words

Approximate, Dadda, Multiplier, Verilog, Speed

Cite This Article

"Implementation of Power Area Efficient 32-Bit Approximate Multiplier with Improved Accuracy", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.8, Issue 1, page no.636-641, January-2021, Available :http://www.jetir.org/papers/JETIR2101087.pdf

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2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Implementation of Power Area Efficient 32-Bit Approximate Multiplier with Improved Accuracy", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.8, Issue 1, page no. pp636-641, January-2021, Available at : http://www.jetir.org/papers/JETIR2101087.pdf

Publication Details

Published Paper ID: JETIR2101087
Registration ID: 305004
Published In: Volume 8 | Issue 1 | Year January-2021
DOI (Digital Object Identifier):
Page No: 636-641
Country: bhopal, mp, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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