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Published in:

Volume 8 Issue 2
February-2021
eISSN: 2349-5162

Unique Identifier

JETIR2102159

Page Number

1335-1341

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Title

HIGH SPEED AND AREA EFFICIENT VLSI IMPLEMENTATION ON REAL VALUED FFT STRUCTURES

ISSN

2349-5162

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"HIGH SPEED AND AREA EFFICIENT VLSI IMPLEMENTATION ON REAL VALUED FFT STRUCTURES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.8, Issue 2, page no.1335-1341, February-2021, Available :http://www.jetir.org/papers/JETIR2102159.pdf

Abstract

Efficient computation of real-valued fast Fourier transform (RFFT) has received significant attention in recent years due to its several applications in conventional digital signal processing and other emerging areas. In-place RFFT architectures are gaining popularity due to their lower hardware complexity compared with pipeline architectures. In previous method, a design approach is presented to develop an area-delay and energy-efficient architecture for in-place RFFT. Generally, an in-place fast Fourier transform (FFT) structure consists of a butterfly block which performs a set of butterfly operations in every clock cycle. The resolution of memory access conflict is however more challenging for higher butterfly block sizes. Therefore, we have analyzed the data-flow and memory footprint of in-place RFFT architectures for different throughput requirements, and based on that, we have proposed here a strategy to partition the storage unit into several banks of smaller sizes (without increasing the overall memory size) to resolve the memory access conflicts by concurrent data-swapping between the banks. In this paper ,we have designed a new butterfly unit is proposed in which 8 point butterfly unit is implemented by two 4 point FFT unit with simple butterfly structure and low memory requirement. so when compare to the previous method the proposed method consume less area over ahead and less delay. The synthesis and simulation results are verified by using Xilinx ISE 14.7 tool.

Key Words

Fast Fourier transform, in-place computation, real-valued FFT

Cite This Article

"HIGH SPEED AND AREA EFFICIENT VLSI IMPLEMENTATION ON REAL VALUED FFT STRUCTURES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.8, Issue 2, page no. pp1335-1341, February-2021, Available at : http://www.jetir.org/papers/JETIR2102159.pdf

Publication Details

Published Paper ID: JETIR2102159
Registration ID: 305700
Published In: Volume 8 | Issue 2 | Year February-2021
DOI (Digital Object Identifier):
Page No: 1335-1341
ISSN Number: 2349-5162

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Cite This Article

"HIGH SPEED AND AREA EFFICIENT VLSI IMPLEMENTATION ON REAL VALUED FFT STRUCTURES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.8, Issue 2, page no. pp1335-1341, February-2021, Available at : http://www.jetir.org/papers/JETIR2102159.pdf




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