• M.Thejaswini
• V.Mahesh
• Dr.P.Krishna Murthy

In this paper, Adder’s plays major role in multiplications and other advanced processors designs. Adders can be constructed for many numerical representations such as arithmetic and logical operation. The most adders operates on binary numbers. Among the different types of adders, carry select adder is a one of the fastest adder. Carry select adder was designed by using Full adders. This paper presented a Full adder with fault localization for the input bits. By using this scheme, instead of replacing the whole system we can now replace the particular faulty modules. When compare to existing method the proposed method is better in terms of area and delay. Hence the simulations results are verified by using Xilinx ISE 14.7 version.

Concurrent error detection, carry select adder, design for testability

"CARRY SELECT ADDER CONCURRENT ERROR DETECTABLE WITH EASY TESTABILITY", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.8, Issue 3, page no.1854-1859, March-2021, Available :http://www.jetir.org/papers/JETIR2103228.pdf

"CARRY SELECT ADDER CONCURRENT ERROR DETECTABLE WITH EASY TESTABILITY", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.8, Issue 3, page no. pp1854-1859, March-2021, Available at : http://www.jetir.org/papers/JETIR2103228.pdf