• sunguluru Kiran Kumar
• N. Vamsi Praveen
• M.JanardhanaRaju

Real-time implementation of many digital signal processing (DSP) algorithms and multimedia applications are limited by the available speed, energy efficiency, and area requirement of multiplication. The multiplier-free implementation of the constant vector multiplication is reexamined. A novel improved signed digit representation technique is proposed to overcome the two main drawbacks of the current multiplier-free techniques: 1) computational redundancy and 2) circuit irregularity. The fundamental difference between the proposed technique and the existing multiplier-free techniques is a novel optimization framework based on vector decomposition. Experimental results demonstrate that the proposed technique outperforms the existing multiplier-free techniques in less operations and more regular circuit structure. In proposed system we use parallel prefix adder like Brent Kung adder (BKA) for optimizing the performance parameters like area and delay. The proposed multiplication scheme is coded in Verilog HDL and simulated using Xilinx ISE.

Canonical signed digit (CSD), Improved signed digit (CSD), Vector multiplication, Brent Kung Adder (BKA)

"High speed constant vector multiplication based on improved signed digit Approach", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 2, page no.180-185, February-2019, Available :http://www.jetir.org/papers/JETIRAB06033.pdf

"High speed constant vector multiplication based on improved signed digit Approach", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 2, page no. pp180-185, February-2019, Available at : http://www.jetir.org/papers/JETIRAB06033.pdf