• Nanditha M S
• Dr. Vijaya Prakash A M

In VLSI system design, Power consumption and energy dissipation of a circuit have become very crucial factors. There are different techniques to reduce the power and energy consumption of the circuit in which adiabatic technique is one amongthem. The power and energy recovery capability of thecircuits can be optimized using adiabatic technique andpower consumed in VLSI circuits can be reused. SRAM (Static random-access memory) has good speed to access the data but it has more power dissipation. Hence SRAM cell with adiabatic logic has been proposed in both CMOS (180nm and 32nm) and FinFET (32nm) to reduce the power and energy consumption. This adiabatic SRAM cell operatessame as typical 6-T SRAM cell. SCRL (Split level charge recovery logic)is used to design SRAM cell’s latch. The Monte Carlosimulation is also performed forboth CMOS and FINFET technologies using HSPICE and results shows FinFET based SRAM cell has 2.37 times less power consumption as compared to the CMOS based SRAM cell.

Adiabatic logic,SCRL, FinFET, Monte Carlo simulation, HSPICE

"Performance Analysis of CMOS and FinFET Based Adiabatic SRAM Cell at 32nm Technology ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 2, page no.470-473, February-2019, Available :http://www.jetir.org/papers/JETIRAB06081.pdf

"Performance Analysis of CMOS and FinFET Based Adiabatic SRAM Cell at 32nm Technology ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 2, page no. pp470-473, February-2019, Available at : http://www.jetir.org/papers/JETIRAB06081.pdf