• K. Jansi Laksmi
• K. Susmitha
• P. Sandhya
• O.B. Siva kumari
• N. Rajeshkumar

This paper, a high-speed power-efficient VLSI design of a finite field multiplier in GF(2m) is presented. The proposed design has a serial-in parallel-out Structural design and performs the multiplication operation using a reordered normal basis. The main construction block of the multiplier in dynamic logic to reduce the critical path delay. Reduction in dynamic power consumption is achieved by limiting the contention current between the transistor and pull-down network at the beginning of the estimation phase by employ a control circuit. The semicustom layout of the multiplier was realized in 65-nm CMOS technology. The proposed design methodology can also be used in the design of similar FFM possessing regular Structural designs

Dynamic logic, elliptic curve cryptography (ECC), finite field arithmetic, reordered normal basis (RNB), serial-in parallel-out (SIPO) finite field multiplier

"VLSI DESIGN OF DYNAMIC LOGIC BASED SUCCESSIVE FFM ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 2, page no.608-612, February-2019, Available :http://www.jetir.org/papers/JETIRAB06113.pdf

"VLSI DESIGN OF DYNAMIC LOGIC BASED SUCCESSIVE FFM ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 2, page no. pp608-612, February-2019, Available at : http://www.jetir.org/papers/JETIRAB06113.pdf