• I.Suneetha
• P. Neethachowdary
• K.Chethan
• V.Chandrika
• C.DileepKumar

In this short, another twofold counter structure is proposed. Wallace tree multipliers give a power-proficient methodology to rapid duplication. The utilization of rapid 7:3 counters in the Wallace tree decrease can additionally enhance the multiplier speed. And furthermore we actualize 128bit Vedic Wallace multiplier give fast and expends not so much power but rather more productively. Consequently in proposed strategy we create 8X8 Wallace tree multiplier stacker and Vedic Wallace 128X128 piece stacker. These proposed strategies have preferred execution enhancement over 6 TO 3 Bit stacker and 7 TO 3 bit stacker. In existing technique, It utilizes 3-bit stacking circuits, which bunch the majority of the "1" bits together, trailed by a novel symmetric strategy to consolidate sets of 3-bit stacks into 6-bit stacks. The bit stacks are then changed over to paired checks, delivering 6:3 counter circuits with no xor doors on the basic way. This shirking of xor entryways results in quicker plans with effective power and zone usage. In VLSI reenactments, the proposed counters are 30% quicker than existing parallel counters and furthermore expend less power than other higher request counters. Furthermore, utilizing the proposed counter-based Wallace tree multiplier models diminishes inertness and power utilization for 128-piece multipliers.

Counter, high speed, low power, multiplier, VLSI, Wallace tree.

"Implementation of Fast Binary Counters Based on Symmetric Stacking", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 2, page no.625-629, February-2019, Available :http://www.jetir.org/papers/JETIRAB06116.pdf

"Implementation of Fast Binary Counters Based on Symmetric Stacking", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 2, page no. pp625-629, February-2019, Available at : http://www.jetir.org/papers/JETIRAB06116.pdf