• N.N.S Hima Bindu
• T. Gowri

In this paper, a novel architecture is presented for the pulse-triggered D-Flip-Flop in the CMOS 250nm technology. This novel architecture utilizes a transmission gate to control the input data and leakage power. The pulse generator is also modified to reduce the number of required transistors and the clock pulse delay. In addition, pull-up PMOS transistor is controlled by input data to reduce the power dissipation. The proposed architectures have improvement in terms of different architectures that are implemented using 250nm technology to reduce the power delay performance in comparison with different D-Flip-Flop architectures. The proposed D-Flip-Flop architectures are simulated using Top Spice. By using mobile applications, we can implement these architectures in cadence using 90nm technology.

clock pulse delay, Delay performance, leakage power, Pulse-triggered flip-flops, power dissipation, Transmission gate

"Performance analysis of a pulse-triggered D-flip-flops design for ultra-low power applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 2, page no.692-696, February-2019, Available :http://www.jetir.org/papers/JETIRAB06131.pdf

"Performance analysis of a pulse-triggered D-flip-flops design for ultra-low power applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 2, page no. pp692-696, February-2019, Available at : http://www.jetir.org/papers/JETIRAB06131.pdf