• Darshan Mehta
• Naresh Patel

Simulation time, cost and test approaches are the major problems in the mixed-signal verification of a complex System-on-Chip (SoC). In this paper, an equivalent Power On Reset (POR) model has been created using the System Verilog language placed into a mixed-signal Sensor chip. Such a model can be simulate on a digital simulator, which is considerably faster as well as economical than the traditional method using an analog solver. Some verification approaches based on digital methods (Universal verification methodology) are also presented.

POR, Mixed-Signal Verification, System Verilog, UVM

"SYSTEM VERILOG MODEL DEVELOPMENT & VERIFICATION OF POR(POWER ON RESET) IN SENSOR CHIP ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 7, page no.179-184, July-2018, Available :http://www.jetir.org/papers/JETIRC006340.pdf

"SYSTEM VERILOG MODEL DEVELOPMENT & VERIFICATION OF POR(POWER ON RESET) IN SENSOR CHIP ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 7, page no. pp179-184, July-2018, Available at : http://www.jetir.org/papers/JETIRC006340.pdf