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Published in:

Volume 6 Issue 5
May-2019
eISSN: 2349-5162

Unique Identifier

JETIRCQ06036

Page Number

204-207

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Title

Analysis of Low Cost Scan Architectures

ISSN

2349-5162

Cite This Article

"Analysis of Low Cost Scan Architectures", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 5, page no.204-207, May - 2019, Available :http://www.jetir.org/papers/JETIRCQ06036.pdf

Abstract

The current trends necessitate high performance DFT techniques to ensure testability of the manufactured SOC. Along with the benefits; the high performance DFT techniques are also accompanied by some costs. DFT Scan Architectures toll with power, pin, area and timing requirements, just to name a few. This paper aims at analyzing various existing Low cost DFT architectures. In addition, described are the various merits and demerits of the proposed methods. Finally the various performance parameters are compared for each of the architectures in tabular format.

Key Words

Scan architecture, compressed scan, test wrapper, scan chain

Cite This Article

"Analysis of Low Cost Scan Architectures", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 5, page no. pp204-207, May - 2019, Available at : http://www.jetir.org/papers/JETIRCQ06036.pdf

Publication Details

Published Paper ID: JETIRCQ06036
Registration ID: 217265
Published In: Volume 6 | Issue 5 | Year May-2019
DOI (Digital Object Identifier):
Page No: 204-207
ISSN Number: 2349-5162

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Cite This Article

"Analysis of Low Cost Scan Architectures", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 5, page no. pp204-207, May - 2019, Available at : http://www.jetir.org/papers/JETIRCQ06036.pdf




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