UGC Approved Journal no 63975(19)

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Published in:

Volume 6 Issue 5
May-2019
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIRCU06013


Registration ID:
217958

Page Number

63-68

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Title

Design and Simulation of 8-Bit ALU Integrated With 8x8 SRAM Memory Using Hybrid of GDI and SB Technique

Abstract

An 8-bit Arithmetic Logic Unit (ALU) and SRAM is designed by using the hybrid of two techniques i.e. gate diffusion input (GDI) technique and substrate biasing technique (SBT). In this work, ALU consists of multiplexer (4x1 and 2x1) and full adders used to perform logic operations such as OR, AND, XOR, XNOR and arithmetic operations such as Increment, Decrement, Addition and Subtraction. To design multiplexer GDI cells are used and substrate biasing technique is utilized. GDI is used to design full adder AND, OR, XOR, XNOR gates which are then associated to realize ALU. As compared to CMOS techniques this design consume less power, required less surface area, more efficient and faster. Cache memory of Microprocessor and ASICs used large SRAM array can occupy a large portion of the die area. The more than 90% area of SOC in next 10 years projected to occupy by the high density circuits such as SRAM. The large array of fast SRAM helps to raise the performance to optimize the performance of such chips. However, the cost of the chip becomes higher due to the area impact of incorporating SRAM arrays into a chip directly. Hence it is require to minimizing the footprints of SRAM cells. As an outcome, millions of minimum-size SRAM cells are tightly packed, which causes SRAM arrays are densest circuitry on a chip. This project aims to design an 8 bit ALU which is interfaced with the 64 bit SRAM where the inputs and results of ALU operations can be stored. The simulation is carried out using CADENCE VIRTUOSO with gpdk 180nm technology.

Key Words

GDI Technique, ALU, Substrate biasing, cadence VIRTUOSO gpdk 180,6T cell, SRAM, Sense Amplifier, VLSI

Cite This Article

"Design and Simulation of 8-Bit ALU Integrated With 8x8 SRAM Memory Using Hybrid of GDI and SB Technique", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 5, page no.63-68, May 2019, Available :http://www.jetir.org/papers/JETIRCU06013.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Design and Simulation of 8-Bit ALU Integrated With 8x8 SRAM Memory Using Hybrid of GDI and SB Technique", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 5, page no. pp63-68, May 2019, Available at : http://www.jetir.org/papers/JETIRCU06013.pdf

Publication Details

Published Paper ID: JETIRCU06013
Registration ID: 217958
Published In: Volume 6 | Issue 5 | Year May-2019
DOI (Digital Object Identifier):
Page No: 63-68
Country: Chennai, Tamil Nadu, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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