• Mohamed Azeem Hafeez
• Dr. Aziz Musthafa B

the main component of computation model are energy, space, and time. Minimizing them is challenging in building efficient processing design. This work overcomes the problem of using caching utilizing reversible logic circuits (RLC). Further, high communication overhead among cache and main memory affects performance and incurs high heat in VLSI component such as GPU, CPU etc. Thus, limiting or efficient usage of memory resource is most desired. For using RLC, it is important to reduce the delay and wire length of VLSI circuit. This work present an Information processing unit (IPU) using logically reversible circuit using adiabatic reversible Toffoli gate. For minimizing path delay due to presence of faults in circuit design Elmore model is used both at switch level and at wire level and linear model is used at the gates. Further, for bringing tradeoff between memory minimization and delay (processing time) requirement a delay aware rectilinear Steiner minimum tree (RSMT) is created. Experiment are conducted on industrial circuits in the ISPD98 benchmark data. The outcome attained show the proposed model reduces wire length, processing time and memory usage when compared with existing model. Thus, our model aid in improving thread-level and instruction-level parallelization under shared memory environment such as GPU.

Cache memory, Primary memory, Rectilinear Steiner tree, Reversible logic circuit, Slack and Slew constraint, VLSI .

"Optimal memory utilization and wire length minimization for reducing energy consumption of VLSI circuits", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 5, page no.356-363, May 2019, Available :http://www.jetir.org/papers/JETIRCU06071.pdf

"Optimal memory utilization and wire length minimization for reducing energy consumption of VLSI circuits", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 5, page no. pp356-363, May 2019, Available at : http://www.jetir.org/papers/JETIRCU06071.pdf