• M.Ravalika

As compared to conventional inverter topologies like diode clamped and capacitor clamped inverters, the cascaded multilevel inverter has lesser harmonics as well as lower switching stress. The cascaded topology has more number of power switches leading to greater heat losses, larger size, higher cost and more gate drive circuitry. The proposed configuration contains less number of switches and produces lesser harmonics in the output voltage than the cascaded topology. A comparison between four different types of pulse width modulation (PWM) techniques, namely, In-phase disposition (IPD), Anti-phase disposition (APD), Carrier Overlap (CO) and Variable Frequency (VF) PWM methods, has been done. The results have been verified through simulation study in MATLAB/Simulink inorder to select the best PWM method that provides minimum THD in the output voltage. An LC filter has been designed to improve the harmonic profile.

Multilevel inverter, PWM technique, total harmonic distortion, LC filters

"PERFORMANCE OF THREE PHASE II-LEVEL INVERTER WITH REDUCED NUMBER OF SWITCHES USING DIFFERENT PWM TECHNIQUES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 9, page no.476-486, September-2018, Available :http://www.jetir.org/papers/JETIRE006071.pdf

"PERFORMANCE OF THREE PHASE II-LEVEL INVERTER WITH REDUCED NUMBER OF SWITCHES USING DIFFERENT PWM TECHNIQUES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 9, page no. pp476-486, September-2018, Available at : http://www.jetir.org/papers/JETIRE006071.pdf