• Kesavan Gopal

In this paper, a new design and development of Test Jig for CAIR DSP is proposed and implemented. the design, development and productionize the “TestJig” units are to be realized around CAIR ASIC in association with DSP and FPGA with other peripherals and protocol interfaces. The functional demarcations between DSP and FPGA are left to the discretion of designer which covers the interface of various peripherals and interfaces protocols. The functionality of the developed “TestJig” shall be demonstrated for the integrity of peripherals and protocol interfaces by developing necessary test programs. Technicalities as above and proposes to participate in the above mentioned design, development, deliver and warranty as per requirement and is submitting this paper.

CAIR DSP, FPGA, Test Jig, Interface device driver Development.

"Design and Development of Test Jig for CAIR DSP", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 2, page no.199-206, February-2019, Available :http://www.jetir.org/papers/JETIREM06034.pdf

"Design and Development of Test Jig for CAIR DSP", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 2, page no. pp199-206, February-2019, Available at : http://www.jetir.org/papers/JETIREM06034.pdf