• Hitender Kumar Tyagi
• P.J. George

This paper presents a detailed modeling and analysis of trap-assisted gate tunneling in dual-layer high-k gate dielectric structures such as SiO₂/HfO₂ and SiO₂/ZrO₂. The study explores the effects of interface traps, trap density, and temperature on the gate leakage current characteristics of nanoscale MOS devices for sub-45 nm technology node. The analytical model is developed by considering electron injection into dual dielectric layers with a single trap energy level below the conduction band edge. The simulation results show that the incorporation of high-k materials reduces gate leakage significantly compared to single oxide layers, while the presence of traps increases leakage depending on trap density and position. The SiO₂/HfO₂ stack demonstrates the lowest leakage and the best thermal stability, making it a potential dielectric stack for future CMOS scaling.

High-k dielectric, Trap-assisted tunneling, Gate leakage current, Interface traps, Temperature dependence, Dual-layer structure

"Modeling and Analysis of Trap-Assisted Gate Tunneling in Dual-Layer High-k Gate Dielectrics", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.1, Issue 7, page no.749-755, December-2014, Available :http://www.jetir.org/papers/JETIR1701D58.pdf

"Modeling and Analysis of Trap-Assisted Gate Tunneling in Dual-Layer High-k Gate Dielectrics", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.1, Issue 7, page no. pp749-755, December-2014, Available at : http://www.jetir.org/papers/JETIR1701D58.pdf