• Neeraj Gupta

CMOS refer a particular design of digital circuitry design, and that circuit to integrated circuit (chip) of the family process used for implementation. In this paper, we use 0.35µm VLSI technology and compare the power dissipation of CPPLL with the different blocks. PFD (Phase Frequency Detector), Charge Pump, Loop Filter, VCO (Voltage Controlled Oscillator), Frequency Divider. In today’s wireless communication system, greater maximum frequency required by the CPPLL with respect to the digital phones that use these circuit law, power consumption, small size and cost is important design factor of low fabrication. In this paper we take each of these component and design, simulate them using various combination we work to improve the efficiency of the system.

Design Charge-Pump Phase-Locked Loop, TSMC 0.35µm, Power Optimization, CMOS Logic

"DESIGN CHARGE-PUMP PHASE-LOCKED LOOP (CPPLL) USING 0.35µm VLSI TECHNOLOGY", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 5, page no.820-824, May-2018, Available :http://www.jetir.org/papers/JETIR1805556.pdf

"DESIGN CHARGE-PUMP PHASE-LOCKED LOOP (CPPLL) USING 0.35µm VLSI TECHNOLOGY", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 5, page no. pp820-824, May-2018, Available at : http://www.jetir.org/papers/JETIR1805556.pdf