• P. PUSHPALATHA
• SK.JABIDA

The on line transparent test technique for detection of latent hard faults which develop in first input first output buffers of routers during field operation of NOC and also propose fault tolerant solution by introducing shared buffer in router. It provides alternative way in case of detection of faults otherwise used to improve efficiency. The technique involves repeating tests periodically to prevent accumulation of faults. NOC approach has emerged as a promising solution for on chip communications. This proposes an on line transparent test technique for detection of latent hard faults which develop in first input first output buffers of routers during field operation of NOC. The technique involves repeating tests periodically to prevent accumulation of faults. Further this project can be enhanced by using clock skewing technique. Time optimization is main criteria in this enhancement. Modified ring counter decrease total combinational path delay for improved memory organization.

Network On Chip (NOC), First in First Out (FIFO), Built in Self Test (BIST), Dynamic Random Access Memory (DRAM), Clock skewing, Modified ring counter

"DETECT THE PERMANENT FAULTS IN FIFO OF NOC ROUTERS USING SINGLE ADDRESS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 6, page no.628-632, June-2018, Available :http://www.jetir.org/papers/JETIR1806594.pdf

"DETECT THE PERMANENT FAULTS IN FIFO OF NOC ROUTERS USING SINGLE ADDRESS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 6, page no. pp628-632, June-2018, Available at : http://www.jetir.org/papers/JETIR1806594.pdf