UGC Approved Journal no 63975(19)

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Published in:

Volume 5 Issue 6
June-2018
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR1806711


Registration ID:
184234

Page Number

94-101

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Title

To Design 2-bit Magnitude Comparator using CMOS

Abstract

This paper explains the design of a magnitude comparator with four digital input signals and three output signals. The outputs are Greater than, less than and Equals respectively for the four input signals. Low power comparator design is useful to reduce the complexity and increase the computation speed of many digital devices such as ADC, Memory chips etc. The design is done using Full Adder circuit in Mentor Graphics Eldo net tool. The 180 nm technology, file is used for the design of the magnitude comparator. Simulation is done on 0.6 V, 0.8 V, 1 V and 1.2 V respectively. It is found that power is least dissipates in 0.6 V that is 48.82 pW. but it has the longest delay of 53.098 ns. The proposed comparator design is compared with different logic styles such as PTL, Domino logic, and Transmission gates with voltage sweep.

Key Words

Comparator, nano meter technology, Full Adder, Eldo net Tool

Cite This Article

"To Design 2-bit Magnitude Comparator using CMOS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 6, page no.94-101, June-2018, Available :http://www.jetir.org/papers/JETIR1806711.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"To Design 2-bit Magnitude Comparator using CMOS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 6, page no. pp94-101, June-2018, Available at : http://www.jetir.org/papers/JETIR1806711.pdf

Publication Details

Published Paper ID: JETIR1806711
Registration ID: 184234
Published In: Volume 5 | Issue 6 | Year June-2018
DOI (Digital Object Identifier):
Page No: 94-101
Country: Pune, Maharashtra, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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