UGC Approved Journal no 63975

ISSN: 2349-5162 | ESTD Year : 2014
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Published in:

Volume 5 Issue 7
July-2018
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR1808530


Registration ID:
186932

Page Number

357-367

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Title

Implementation of Robust Phase Detector on FPGA for Carrier Recovery Loop in M-PSK Satcom Receivers

Abstract

In this paper, we present the study of a Non Data-Aided (NDA) robust Self-Normalizing Phase Detector (SNPD) for an M-PSK coherent receiver, development of design flow for SNPD, development of customized Xilinx FPGA board and implementation of SNPD on this FPGA board. The implemented structure is a self-normalizing modification of the Mth order nonlinearity detector. A design flow is developed and efficient VHDL coding is done for all the modules and simulation results observed. Integrating the implemented PD with M-PSK demodulator, the overall performance is verified on Chipscope Pro Analyzer and finally validating with an experimental test set up. The main issue in a Decision Directed (DD) PD is sensitivity to AGC amplitude variations. Presently DDPD is widely used in SATCOM applications. The implemented SNPD is robust to Automatic Gain Control (AGC) variations. The concern with Mth order nonlinearity detector is that its large dynamic range makes it unfeasible for fixed point implementation, whereas the implemented SNPD has limited dynamic range and therefore requires lesser resources. It occupies only 1.2 % area of total slices of Spartan 6 FPGA, making it suitable to implement in FPGA or ASICbased hardware. The implemented SNPD has been tested for AGC variations.

Key Words

Satellite Receiver, Carrier Synchronization, recovery loop, PD, M-PSK, AGC, FPGA

Cite This Article

"Implementation of Robust Phase Detector on FPGA for Carrier Recovery Loop in M-PSK Satcom Receivers", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 7, page no.357-367, July-2018, Available :http://www.jetir.org/papers/JETIR1808530.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Implementation of Robust Phase Detector on FPGA for Carrier Recovery Loop in M-PSK Satcom Receivers", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 7, page no. pp357-367, July-2018, Available at : http://www.jetir.org/papers/JETIR1808530.pdf

Publication Details

Published Paper ID: JETIR1808530
Registration ID: 186932
Published In: Volume 5 | Issue 7 | Year July-2018
DOI (Digital Object Identifier): http://doi.one/10.1729/Journal.18198
Page No: 357-367
Country: Ahmedabad, Gujarat, India .
Area: Engineering
ISSN Number: 2349-5162


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