• Shikha Gangwani

Address Decoder is an important digital block in SRAM which takes up to 50% of the total chip access time and notable amount of the total SRAM power in normal read/write cycle. To design address decoder need to consider two objectives, first selecting the good circuit technique and second sizing of transistors in circuit. Novel address decoder circuit is presented and analyzed in this paper. Address decoder using NAND-NOR alternate stages with predecoder and replica inverter chain circuit is proposed and compared with traditional and universal block architecture, using UMC 90nm CMOS technology.

Access Time, Block Architecture, Decoder, CMOS, SRAM

"Design and analysis of a 5:32 Address decoder for a high speed SRAM based", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 8, page no.695-700, August-2018, Available :http://www.jetir.org/papers/JETIR1808858.pdf

"Design and analysis of a 5:32 Address decoder for a high speed SRAM based", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 8, page no. pp695-700, August-2018, Available at : http://www.jetir.org/papers/JETIR1808858.pdf