• Chakravarthy Shreya
• S.Nagi Reddy
• P.Sharmila Rani

This paper describes the implementation of 10 bit high speed low offset and low kickback noise dynamic latch comparator with preamplifier in 65nm CMOS technology. Dynamic latch comparator which uses a positive feedback mechanism to generate the analog input signal to a full scale digital level. Kick back noise and offset voltage are the parameter which effects its performance, these can be reduced by playing preamplifier before dynamic latch comparator. The simulations of preamplifier based dynamic latch comparator are performed at 6 GHZ maximum clock frequency, with power consumption of 3.24mw at 1.2v supply voltage and offset voltage is reduced to 1.4mv. Monte Carlo simulations are carried out with N no of runs (N=100) where standard deviation and mean values are obtained.

ADC, CMOS, Kick Back Noise, Offset Voltage

"High Speed Low Offset Low Kick Back Noise Dynamic Latch Comparator for ADC", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 9, page no.967-972, September-2018, Available :http://www.jetir.org/papers/JETIR1809650.pdf

"High Speed Low Offset Low Kick Back Noise Dynamic Latch Comparator for ADC", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 9, page no. pp967-972, September-2018, Available at : http://www.jetir.org/papers/JETIR1809650.pdf