• AMUTHA A
• KEERTHANA PRIYAA A
• SIVAKUMAR S A

The Watermarking is an intellectual property (IP) protection technique. It can protect field-programmable gate array (FPGA) IPs from infringement. IP protection of hardware designs is the most important requirement for many FPGA intellectual property vendors. Digital watermarking has become an innovative technology for IP protection in recent years. This paper proposes the publicly verifiable watermarking for intellectual property protection in FPGA design. The chaos-based zero knowledge verification protocol is used in this watermarking detection technique. The time stamping is also used and it can resiliently resist the sensitive information leakage and embedding attacks, and is thus robust to the cheating from the prover, verifier, or third party. The zero-knowledge protocol proposed in this paper is implemented by MATLAB R2014a in which C programming language is used in it and ModelSim 10.5b in which VHDL coding is used in it, are running on a PC. The synthesis tool Xilinx ISE 14.5 is also used to verify and implement the watermarking scheme.

Intellectual property (IP) protection, field-programmable gate array (FPGA), publicly verifiable watermarking, zero-knowledge protocol.

"Watermarking Technique for Intellectual Property Protection in FPGA Design", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 10, page no.253-264, October-2018, Available :http://www.jetir.org/papers/JETIR1810734.pdf

"Watermarking Technique for Intellectual Property Protection in FPGA Design", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 10, page no. pp253-264, October-2018, Available at : http://www.jetir.org/papers/JETIR1810734.pdf