• Dhana Prasad Duggapu
• Rajana Rajesh

In this paper a new basic unit is proposed for multilevel inverters. The proposed basic units are used as building blocks to form a cascaded multilevel inverter i.e. the proposed topology consists of cascaded basic units and it uses lower number of switching devices and gate driver circuits. The design of proposed topology consists of mainly two parameters: the number of cascaded basic units and the number of dc sources in each basic unit. These two parameters can be used to design the desired multilevel inverter based on the operational conditions. Therefore the proposed topology offers good flexibility in designing. The comparison results with some recently introduced topologies showed that the proposed topology effectively reduces the components count. The simulation results obtained in MATLAB /SIMULINK as well as the experimental results of a 31-level inverter are presented and verified its performance.

Total harmonic distortion, Multi-Level Inverter, Flying capacitor, Induction Motor and PWM Technique.

"A new topology of 31-level Multi level Inverter with Induction Motor", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 3, page no.1902-1909, March-2020, Available :http://www.jetir.org/papers/JETIR2003272.pdf

"A new topology of 31-level Multi level Inverter with Induction Motor", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 3, page no. pp1902-1909, March-2020, Available at : http://www.jetir.org/papers/JETIR2003272.pdf